This invention generally relates to removal of polymer residues following an etching process and more particularly to a method for protecting a wafer backside to prevent etching damage in a wet polymer stripping (PRS) process whereby polymer residues are removed following a metal etching process.
In the fabrication of semiconductor devices multiple layers are required for providing a multi-layered interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal conductor runs or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The profile of a hole is of particular importance since that it exhibits specific electrical characteristics when the contact hole or via is filled with a conductive material. In addition, metal interconnect lines may be formed by selectively anisotropically etching away areas (gaps) in a layer of metal to leave metal interconnect lines which are subsequently covered with a layer of dielectric insulating material to fill the gaps.
In anisotropic etching processes, such as those using halocarbon containing plasmas, polymer deposition on the sidewalls and bottom surface of the feature being etched occurs simultaneously with the etching of the oxide or the metal, as the case may be. Surfaces struck by the ions at a lower rate tend to remove the nonvolatile polymeric residual layer at a lower rate, thereby at steady state, leaving a layer of nonvolatile polymeric or metal-polymeric residue on surfaces such as the sidewalls of the etched features, thereby protecting such surfaces against etching by the reactive gas. As such, etching is performed preferentially in a direction perpendicular to the wafer surface since the bottom surfaces etch at a higher rate than the polymeric residue containing sidewalls (i.e., anisotropic etching). If metal is being etched, for example, in etching metal lines, metal will simultaneously deposit with the polymer thus forming a metal-polymer residue on the sidewalls of the etched opening.
In a typical process, for example, an overlying photoresist layer is photolithographically patterned to anisotropically etch the semiconductor features in an underlying layer, for example a metal layer for metal interconnect line etching or an insulating dielectric layer for etching damascene features such as vias or contact holes. After the features are etched, the photoresist mask which remains overlying the upper surface of the etched features may be removed by a reactive ion etch (RIE) process also referred to as an ashing process, for example, carried out in a quartz chamber using a plasma of O2 or a combination of CF4 and O2 to etch the photoresist material.
It has been the practice in the art to remove at least a portion of the photoresist in-situ by an ashing process following an RIE etching procedure where metal is exposed, for instance after anisotropically etching the metal conductive layer, since exposure of the metal to atmospheric conditions can cause metallic corrosion. In such an in-situ ashing process, the photoresist removal may take place by a reactive ion etching (RIE) method using an oxygen containing plasma in an ashing chamber module of a multiple chamber metal etcher.
A processing difficulty arises, however, when a metal-polymer residue forms upon etching a semiconductor feature. In a typical RIE etching process, for example, in etching via openings, etching takes place through the inter-metal dielectric (IMD) layer to expose an underlying metallic contact. Typically the metallic portion is over etched to assure adequate contact of the via opening (which will later be filled with a metallic material) with the underlying metal contact layer. As a result, during the etching process, a metal-polymer residue is formed on the sidewalls of the etched opening that cannot be removed by the RIE ashing process.
Further, the RIE ashing process to remove the overlying photoresist may tend to oxidize the metal-polymer residue formed on the sidewalls of an etched opening thereby making it even more resistant etching in an RIE ashing process. As a result, the metal-polymer residue formed on the sidewalls of an etched opening cannot be successfully removed by an in-situ ashing process and must be additionally cleaned by an ex-situ wet etching process, for example, a wet polymer strip process (PRS).
For example, in a typical wet polymer strip process (PRS) bench configuration wafers are transferred for processing at one or more wet chemical bench process lines. The wafers are typically sequentially immersed in various solutions for a period of time including a primary solvent (wet etching solution) of, for example, ACT available from Ashland Chemical and composed of DMSO (Dimethyl-sulphur-oxide), MEA (Mono-Ethyl-Amine) and catechol typically provided at an elevated temperature. The process wafers are then typically immersed in a neutralizing intermediate solvent solution, for example, n-methyl pyrrolidone (NMP) followed by rinsing solutions of deionized water.
One problem with the prior art wet chemical polymer stripping process is that the wet etching solution including, for example, ACT etches the exposed silicon on the backside of the process wafer. As a result, the backside of the process wafer experiences preferential etching, for example, believed to be related to the dipping or immersion process in the etchant solution carried out in the wet chemical polymer stripping process. As a result, the backside of the process wafer surface is adversely affected by the preferential etching causing difficulties and errors in subsequent photolithographic photomasking patterning steps requiring a level or flat backside surface. For example, due the non-flatness of the process wafer backside following a wet chemical polymer stripping process, leveling difficulties are experienced in the photomasking process leading to defocusing of the photomasked pattern on the process surface. Consequently, semiconductor wafer yields are reduced and wafer manufacturing quality suffers.
There is therefore a need in the semiconductor processing art to develop a method whereby the backside of semiconductor process wafers are protected during a wet chemical polymer stripping process thereby preserving wafer backside flatness.
It is therefore an object of the invention to provide a method whereby the backside of semiconductor process wafers are protected during a wet chemical polymer stripping process thereby preserving wafer backside flatness while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for protecting a silicon semiconductor wafer backside surface during a wet etching process for removing polymer containing residues from a wafer process surface.
In a first embodiment, the method includes providing a silicon semiconductor wafer having a process surface and a backside surface said process surface including metal containing features said process surface at least partially covered with polymer containing residues and said backside surface including exposed silicon containing areas; forming an etching resistant oxide layer over the exposed silicon containing areas; and, subjecting the silicon semiconductor wafer to a series of cleaning steps including a wet etchant corrosive to the exposed silicon containing areas whereby the etching resistant oxide layer protects the backside surface from wet etching.
These and other embodiments, aspects and features of the invention are better understood from a detailed description of preferred embodiments of the invention which are described in conjunction with the accompanying Figures.